A number of known circuit configurations require high-ratio-accuracy capacitors. Thus, for example, in an article entitled "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I," Journal of Solid-State Circuits, Volume SC-10, No. 6, pages 371-379, December 1975, the use of a binary-weighted capacitor array to perform high-speed successive approximation conversion is described. As stated on page 373 of the article, "the optimization of the ratio accuracy [of the capacitors] in the array is a prime consideration."
Additionally, high-ratio-accuracy capacitor geometries are required for so-called switched capacitor filter units. (See "Analog Sample-Data Filters," IEEE Journal of Solid-State Circuits, Volume SC-7, No. 4, pages 302-304, August 1972, for a description of such units.) In filters of this type, capacitor ratio accuracies of less than .+-.1% are frequently specified.
Fabrication of matched-ratio capacitors in integrated-circuit form typically involves a processing sequence that includes various etching steps. During such a sequence, deviations from an optimum specified ratio frequently occur. Thus, for example, under- or over-etching during the capacitor fabrication process can cause unacceptable deviations from the specified ratio.
Ratio errors arising from variations in the etching steps utilized to fabricate integrated circuit capacitors can be minimized. As described in the first of the above-cited articles, this can be done, for example, by interconnecting identical discrete capacitor units in parallel (see FIG. 6 on page 374 of the cited article). This interconnected array forms a relatively large capacitance-value unit. In turn, the relatively small capacitance-value unit of a matched pair of ratio capacitors comprises one or more such identical units. In this way, a matched pair of units whose values are related by an integral ratio is provided. The capacitor units of the pair are characterized by respective perimeters and areas which are also each related by the specified ratio. Significantly, the prescribed capacitance ratio of such a pair of units is substantially insensitive to etching variations that occur during the capacitor fabrication process.
The above-described interconnected-array approach of fabricating ratio capacitors in integrated circuit form is characterized by several disadvantages. First, the yield and therefore the cost of such an array suffer from the requirement that for each capacitor unit in the interconnected array a separate pair of microminiature contact windows must be formed. For high-ratio arrays, this obviously becomes a burdensome requirement. Second, especially when a relatively high ratio of capacitance values is specified, the parasitic capacitance of the array tends to become unacceptably large and unpredictable. Third, the interconnected array approach does not lend itself to processing-insensitive fabrication of capacitor units having nonintegral ratios.
In view of the above, continuing efforts have been made to attempt to devise improved ratio-capacitor geometries for implementation in integrated-circuit form. It was recognized that such improved geometries, if available, would improve the cost and performance of the overall circuit configurations of which the capacitors are important constituent elements.